Verification Engineer
⚲ Warszawa
Do uzgodnienia
Wymagania
- SystemVerilog
- UVM
- Specman
- VCS
- Xcelium
- ModelSim
- Questa
Opis stanowiska
Nasze wymagania:
B.Sc. / M.Sc. / Ph.D. in Electrical Engineering, Computer Engineering, or related field.
5+ years of hands-on VLSI verification experience in an industry setting.
Strong proficiency in SystemVerilog and UVM methodology (environments, agents, sequences, scoreboards).
Strong proficiency in Specman language & methodology
Experience with industry simulation tools: VCS, Xcelium, ModelSim/Questa.
Solid understanding of digital design fundamentals, RTL coding, and microarchitecture concepts.
Familiarity with assertion-based verification (SVA) and coverage-driven verification
O projekcie:
The ideal candidate will be responsible for verifying the functional correctness of complex digital IP blocks and SoCs using industry-standard methodologies and tools. You will work closely with design, architecture, and software teams to deliver high-quality, silicon-proven designs.
Zakres obowiązków:
Develop and maintain constrained-random UVM testbenches for RTL blocks and fullchip verification.
Write functional coverage models and coverage closure plans to drive verification completeness.
Author and execute directed and random test scenarios targeting corner cases and protocol compliance.
Debug simulation failures, identify root causes in RTL, and collaborate with designers on fixes.
Develop verification plans (VPlans) based on micro-architecture specifications and track sign-off metrics.
Contribute to regression infrastructure, CI/CD pipelines, and EDA tool flow scripting.
Participate in design reviews, spec reviews, and silicon bringup activities.
B.Sc. / M.Sc. / Ph.D. in Electrical Engineering, Computer Engineering, or related field.
5+ years of hands-on VLSI verification experience in an industry setting.
Strong proficiency in SystemVerilog and UVM methodology (environments, agents, sequences, scoreboards).
Strong proficiency in Specman language & methodology
Experience with industry simulation tools: VCS, Xcelium, ModelSim/Questa.
Solid understanding of digital design fundamentals, RTL coding, and microarchitecture concepts.
Familiarity with assertion-based verification (SVA) and coverage-driven verification
O projekcie:
The ideal candidate will be responsible for verifying the functional correctness of complex digital IP blocks and SoCs using industry-standard methodologies and tools. You will work closely with design, architecture, and software teams to deliver high-quality, silicon-proven designs.
Zakres obowiązków:
Develop and maintain constrained-random UVM testbenches for RTL blocks and fullchip verification.
Write functional coverage models and coverage closure plans to drive verification completeness.
Author and execute directed and random test scenarios targeting corner cases and protocol compliance.
Debug simulation failures, identify root causes in RTL, and collaborate with designers on fixes.
Develop verification plans (VPlans) based on micro-architecture specifications and track sign-off metrics.
Contribute to regression infrastructure, CI/CD pipelines, and EDA tool flow scripting.
Participate in design reviews, spec reviews, and silicon bringup activities.
🔍 Dekoder Ogłoszenia
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deliver high-quality, silicon-proven designs
Oczekuje się, że kandydat będzie miał doświadczenie w tworzeniu projektów, które przeszły pomyślnie testy krzemowe, co sugeruje nacisk na niezawodność i dojrzałość procesu weryfikacji.
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Debug simulation failures, identify root causes in RTL, and collaborate with designers on fixes
Oznacza to, że kandydat będzie musiał aktywnie uczestniczyć w procesie debugowania, co może być czasochłonne i wymagać głębokiego zrozumienia zarówno logiki RTL, jak i samego środowiska weryfikacyjnego.
🟡
Contribute to regression infrastructure, CI/CD pipelines, and EDA tool flow scripting
Wymaga to nie tylko umiejętności weryfikacji, ale także wiedzy z zakresu automatyzacji procesów, co może oznaczać dodatkowe obowiązki poza czystą weryfikacją funkcjonalną.
🟡
track sign-off metrics
Kandydat będzie odpowiedzialny za monitorowanie i raportowanie postępów weryfikacji, co wymaga dobrej organizacji i umiejętności analizy danych.